In order to be competitive, semiconductor manufacturers strive to reduce the time to market for design, manufacture, validation and delivery of integrated circuit (IC) devices. In addition, to time, significant development has been invested in making each step in the process more economical, such as validation testing. In particular, automated test equipment (ATE) is programmed to support, stimulate and sense operating parameters of a given IC device. A handler positions each IC device for testing by the ATE, and the testing results in separately binning good and bad IC devices.
Significant hardware investment has been made in ATE and handler equipment suitable for validation testing of a wide range of IC devices. For example, ATE incorporates a wide array of capabilities for providing radio frequency (RF) signals and sensing, various digital signal inputs and outputs, etc. In order to multiply the throughput of such ATE, typically each ATE can simultaneously test a plurality of IC devices, supported by handlers designed for simultaneously placing and retrieving these IC devices under test (DUT). A degree of standardization in such equipment occurs in order to make them more economical and to reduce the training time required for programmers of such ATE and handlers. To that end, each validation testing effort has to be adapted to the electrical capabilities and constraints of the ATE and to the hardware configuration and limitations of the handler.
A typical device interface board (DIB) design used by all semiconductor manufacturers consists of a printed circuit board (PCB) with all the essential supporting components and circuits along with a test socket. Test software is then written to provide instructions to the ATE on the stimulus to provide and the measurements to make. Ultimately, a decision will be made to distinguish a good part from a bad part, also commonly termed as binning. A DIB may come in different shapes and sizes, but the concept is the same.
Although standardization of ATE and handlers is desirable, a challenge is presented by an ongoing effort to make IC devices smaller and more capable, which often means increasing complexity in interfacing to the IC device (e.g., increased pin count, increased numbers of inputs and outputs, etc.). This increased complexity is accommodated by designing a custom DIB that mounts to the ATE for providing one or more custom test sites for receiving IC devices from the handler. A printed circuit board (PCB) of the DIB is increasing in the number of layers (e.g., 22, 24, etc.) that are required to provide the required connectivity and supporting signals. Area available for mounting support components (e.g., lumped electronic components) is generally limited to an underside of the PCB because an upper surface is limited by clearance for the handler and for docking sites.
Another challenge is that the multiple test sites on the DIB require traces that perform identically so that shared signals test each IC device identically. The large size of the DIB and the traces, with some by necessity being routed differently in length, make such designs problematic.
Even if these constraints can be satisfied, the large size of the PCB for the DIB makes design of each layer time consuming, with current benchmarks indicating that an experienced design engineer requires one day per layer. Thus, it is not uncommon for the length of time required to design a DIB to become the critical path rather than the manufacture of a new IC device. This is increasingly a challenge, as conventional DIBs need to have additional layers to support complex IC devices.
Yet another challenge is that manufacturing costs are based upon assumptions that each ATE is being operated at capacity. However, when one test site fails on a multiple test site DIB, the rate of validation testing goes down. Each DIB has a cost that is prohibitive in provisioning spares and is expensive to diagnose and repair. For example, it is common for a DIB to currently cost $30,000 for a replacement.
Towards the end of the hardware and software development cycle, engineers need to perform a Gage study to determine repeatability (i.e., data variation when tested multiple times) and reproducibility (i.e., data reproduction using multiple correlated testers), which provides as indicators of quality and stability of the final test solution. Sample data is collected across multiple ATE testers, DIBs, and devices to derive the mean and standard deviation from which a user can determine the acceptability of the final test solution. In the detailed description, embodiments will be presented to improve overall performance by yielding better Gage results. Improvements in performance as shown in a Gage study will correlate to the speed of which a product can be brought to market/production as well as the quality of the test solution, all of which fortifies a company's leadership in a specific market space. It is thus a challenge to make corrections to satisfy a Gage study if a change to the DIB is necessary.